The present invention relates to semiconductor devices in which characteristic evaluation transistors are provided in addition to an actually used transistor, and methods for evaluating characteristics of the semiconductor devices.
Conventionally, devices for checking characteristics, capable of measuring contact resistance, the threshold voltage and I–V characteristics of transistors, and other characteristics, have been provided in semiconductor devices, so that, e.g., characteristics that are out of the ordinary due for example to fluctuations in fabrication qualities and to processing difficulties can be easily checked without performing a probe testing of the product (see for example Japanese Laid-Open Publication (abstract) No. 2000-214228.)
FIGS. 11A through 11C respectively illustrate a circuit diagram, plan view, and cross sectional view of an evaluation portion of a prior art characteristic evaluation transistor.
As shown in FIGS. 11A and 11B, the evaluation portion includes a MIS transistor 101, a source pad 102, a drain pad 103, and a gate pad 104. The MIS transistor 101 is a characteristic evaluation transistor. The source pad 102 is connected to a source region 105 of the MIS transistor 101. The drain pad 103 is connected to a drain region 106 of the MIS transistor 101. The gate pad 104 is connected to a gate electrode 107 of the MIS transistor.
As shown in FIG. 11C, a trench isolation (STI) 110 and the source and drain regions 105 and 106 are defined in a semiconductor substrate 100, which is a Si substrate. The trench isolation 110 defines an active region. The source and drain regions 105 and 106 are both doped with impurities. The MIS transistor further includes a gate insulating film 108 formed on the active region, the gate electrode 107 formed on the gate insulating film 108, and a sidewall 109 formed on the lateral faces of the gate electrode 107. Formed on the semiconductor substrate 100 are an interlayer dielectric film 111 and plugs 112. The interlayer dielectric film 111 covers the gate electrode 107, the sidewall 109 and other portions. The plugs 112 go through the interlayer dielectric film 111 to reach the source and drain regions 105 and 106. The source pad 102, the drain pad 103, and the gate pad 104 are formed on the interlayer dielectric film 111 and connected via the plugs 112 to the source region 105, the drain region 106, and the gate electrode 107, respectively.
As semiconductor devices have been downsized, both the gate length and gate width of MIS transistors in the semiconductor devices have been also reduced. Consequently, random variations in various characteristics of the MIS transistors caused due for example to variations in impurity concentration distribution and in processing accuracy have become more manifest.
On the other hand, considering standby current and gate delay in an entire semiconductor integrated circuit, an enormous number of—millions of—devices (MIS transistors) involve these properties, so that such random variations are counteracted. As a result, variations (standard deviation) in various kinds of characteristics of the semiconductor integrated circuit are relatively small.
Therefore, when evaluation is performed using a conventional characteristic evaluation portion such as mentioned above, the obtained evaluation results indicate variations greater than actual variations in the characteristics of the semiconductor integrated circuit. In other words, the obtained results do not typify the distribution of the characteristics of the semiconductor integrated circuit proper, as a result of which manufacturing conditions might be controlled too strictly.